问题描述:

Can any one explain what each value in ranges property represent.

my_pcie_0: [email protected] {

#address-cells = <1>;

#size-cells = <1>;

compatible = "mypcie";

device_type = "pcie";

reg = < 0x40000000 0x00100000 >;

ranges = < 0x02000000 0 0xf0000000 0xf00000000 0x0 0x08000000>;

}

网友答案:

This question has been up for a while but I ran into the same issue and found the answer after searching for a while.

my_pcie_0: [email protected] {
    #address-cells = <1>;
    #size-cells = <1>;
    compatible = "mypcie";
    device_type = "pcie";
    reg = < 0x40000000 0x00100000 >;
    ranges = < 0x02000000 0 0xf0000000 0xf00000000 0x0 0x08000000>;
} 

In the ranges field the first three values specify the address on the PCI bus to be mapped in.

0x02000000 0 0xf0000000

However the device tree treats PCI address translations as a special case where the first value is a bitfield instead of an address. In this case "0x02000000" would specify a non-prefetchable 32-bit memory space.

This leaves "0 0xf0000000" as the high and low parts of the 64-bit PCI address to be mapped in, since the high part is 0, the actual address is 0xf00000000.

The fourth value specifies the address on the CPU's bus to map the segment of the PCI bus into. It is 32-bits on a 32-bit processor.

0xf00000000

The fifth and six values specify the size of the segment to map in. In this case a 128MB segment.

0x0 0x08000000

Knowing this it appears that your cell sizes are incorrect, They should instead be 3 for the address cells to cover a 64-bit PCI address value plus the 32-bit bitfield and 2 for the 64-bit size value. The 32-bit size of the CPU address is inherited from the parent.

#address-cells = <3>;
#size-cells = <2>;

Here's a more in-depth explanation on PCI address translation

网友答案:

This is from the documentation:

ranges = <0 0  0x10100000   0x10000     // Chipselect 1, Ethernet
              1 0  0x10160000   0x10000     // Chipselect 2, i2c controller
              2 0  0x30000000   0x1000000>; // Chipselect 3, NOR Flash
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