问题描述:

I'm in work placement and I have this subject in VHDL : Measurement system of response time of computer monitor.

To succeed I thought about to put a photodiode in front of the monitor and switch in black and white every second the monitor to known the response time.

But I don't know really how to make that, I use a spartan 3 connected at the monitor by VGA.

I right a program I'm not sure if it's right, (I think it's wrong). I show you my program :

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL

USE IEEE.NUMERIC_STD.ALL

ENTITY Counter IS

PORT(clk, rst : IN STD_LOGIC;

sync, PhD : IN STD_LOGIC;

s : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));

END ENTITY Counter;

ARCHITECTURE Main OF Counter IS

SIGNAL q : UNSIGNED (3 DOWNTO 0);

BEGIN

s <= STD_LOGIC_VECTOR(q);

PROCESS (clk, rst) IS

BEGIN

IF rst='1' THEN

q<=(OTHERS => '0');

ELSIF RISING_EDGE(clk) THEN

IF sync='0' THEN

q=q;

ELSIF sync='1' THEN

IF PhD='0' THEN

q<=q+1;

ELSIF PhD='1' THEN

q=q;

END IF;

END IF;

END IF;

END PROCESS;

END ARCHITECTURE Mai

n;

Tell me if you need something more maybe I forgot something. And tell me what you thing about my program.

网友答案:

What you wrote is a counter that is incremented in each clock cycle that sync is 1 and phd is 0. Without knowing your exact requirements, it is difficult to say whether this is what you want or not.

If you want to determine the amount of time between sync going high and phd going high, you should set q to 0 when sync=0. This will cause the counter to start from 0 each time sync goes high.

You should probably also increase the width of q, depending on how fast your clock is. Currently it has only 4 bits, meaning it will wrap back to 0 every 16 cycles. Given typical clock frequencies (e.g. 100 MHz), this is less than a microsecond. To count for one second at 100 MHz, you would need a counter of at least 27 bits.

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