问题描述:

I am working on a project in which I need for generate the component with variable downto values. Following is the top entity code:

-----------------------------------------------------------

library IEEE;

use IEEE.std_logic_1164.all;

use work.calc_const.all;

--Additional standard or custom libraries go here

entity display_calc is

port(

--You will replace these with your actual inputs and outputs

-- Input

s1_set : in std_logic_vector(DIN1_WIDTH-1 downto 0);

s2_set : in std_logic_vector(DIN2_WIDTH-1 downto 0);

s3_set : in std_logic_vector(OP_WIDTH-1 downto 0);

button_start : in std_logic;

--Output

hex0_set : out std_logic_vector(((DOUT_WIDTH/4)*7)-1 downto 0);

overflow_led : out std_logic;

sign_led : out std_logic

);

end entity display_calc;

architecture structural of display_calc is

--Signals and components go here

component calculator is

port(

--Inputs

DIN1 : in std_logic_vector (DIN1_WIDTH - 1 downto 0);

DIN2 : in std_logic_vector (DIN2_WIDTH - 1 downto 0);

operation : in std_logic_vector (OP_WIDTH - 1 downto 0);

start : in std_logic;

--Outputs

DOUT : out std_logic_vector (DOUT_WIDTH - 1 downto 0);

overflow : out std_logic;

sign : out std_logic

);

end component;

component leddcd is

port(

data_in : in std_logic_vector(3 downto 0);

segments_out : out std_logic_vector(6 downto 0)

);

end component;

signal Input_Decoder : std_logic_vector(DOUT_WIDTH-1 downto 0);

begin

Calc_1122: calculator port map (

DIN1 => s1_set,

DIN2 => s2_set,

operation =>s3_set,

start => button_start,

DOUT => Input_Decoder,

overflow => overflow_led,

sign => sign_led

);

-- This section I want to be in a loop so that I don't have to write the values again and again for variable inputs

decoder_1_11 : leddcd port map(

data_in => Input_Decoder(11 downto 8),

segments_out => hex0_set(20 downto 14)

);

decoder_2_21 : leddcd port map(

data_in => Input_Decoder(7 downto 4),

segments_out => hex0_set(13 downto 7)

);

decoder_3_31 : leddcd port map(

data_in => Input_Decoder(3 downto 0),

segments_out => hex0_set(6 downto 0)

);

end architecture structural;

-------------------------------

SO I have commented above which part I want to be in code format I have tried a lot using for generate statement but the problem I am coming across is for generate I can't use multiple values I have to use single variable, I also don't know that whether my approach is correct or not that I have to use for generate statement or this problem can be solved by other statements.

Thanks in advance for the help.

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