Verilog实现串/并行加法器

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实现两个N位二进制数dataa、datab的乘积,用简单的方法计算就是利用移位操作来实现。dataa进行位扩展左移累加的操作,datab不便右移的操作。

module Multiply(

clk,rst,

dataa,datab,

dout

);

input clk;

input rst;

input [7:0] dataa;

input [7:0] datab;

output reg[15:0] dout;

parameter s1 = 0,s2=1,s3=2;

//reg [7:0]dataareg;

reg [7:0]databreg;

reg [1:0]state;

reg [15:0]tmp;

reg [15:0]dreg;

reg [2:0]count;

always@(posedge clk or negedge rst)

if(!rst)

begin

tmp<=16'b0;

databreg<=8'd0;

state<=0;

//state<=s1;

end

else

case(state)

s1:begin

//tmp<={{8{dataareg[7]}},dataareg};

dreg<=16'd0;

count<=3'd0;

tmp<={{8{dataa[7]}},dataa};

//$dispaly("number %d",tmp);

state<=s2;

databreg<=datab;

end

s2:begin

if(count==7)

state<=s3;

else begin

if(databreg[0]==1)

dreg<=tmp+dreg;

//else

databreg<=databreg>>1;

tmp <= tmp<<1;

//$

//$dispaly("number %d",tmp);

count =count+1;

state<=s2;

end

end

s3:begin

dout<=dreg;

state<=s1;

end

endcase

endmodule

 


选择器件是cycloneII系列

环境是:quartusII11.0

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