A clock domain crossing occurs whenever data is transferred from a flop driven by one clock to a flop driven by another clock.
Signal A is launched by the C1 clock domain and needs to be captured properly by the C2 clock domain. Depending on the relationship between the two clocks, there could be different types of problems in data transferring.
It refers to signals that do not assume stable 0 or 1 states for some duration of time. In a multi-clock design, metastability cannot be avoided but the detrimental effects of metastability can be neutralized.